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Silicon DV engineer

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Ursus

2021-12-03 08:51:21

Job location Sunnyvale, California, United States

Job type: fulltime

Job industry: Other

Job description

Job Title: Silicon DV engineer
Location: Sunnyvale, CA
Duration: 1 Year

Summary:
Power and performance modeling or DV (C, system C, system Verilog, or matlab)
Strong DV background (test plan development, test writing, UVM)
Experience with low power verification (UPF)
Experience with both static (i.e. VC LP) and dynamic (i.e. VCS NLP) power-aware verification flows
Duties:
Responsible for low power verification including both dynamic and static verification
Write and augment existing testplans.
Implement testbench and scoreboards / checkers.
Implement test sequences as per plan and debug failures
Achieve 100% functional, code, and power coverage
Work closely with designers, micro architects & f/w to resolve issues
Ability to communicate & articulate clearly progress / issues with project leads

Must Have:
7+ years of proven experience as a DV engineer
Implied: Candidate will have hands on Experience with executable test plans and Coverage Driven verification
Hands on experience with SV (SystemVerilog) and UVM (Universal Verification Methodology)
Hands on Experience with Synopsys VCS / Verdi or Cadence Incisive tools
Experience with UPF based simulation flow
2+ Years of experience with C/C++

Nice to Have
Power and performance FPGA validation
Hifi4, TIE, CNN, DSP, fixed point, floating point, SONICS, python.
Experience with Power Aware GLS flow
Tcl and Python (or similar) scripting language
ASIC design experience
Experience in formal property verification of complex compute blocks like DSP, CPU or HW accelerators
Experience with complex SoCs
Knowledge of coverage merging across simulation and formal
MSEE/CS or equivalent experience

Education
Must Have: Bachelor degree in Electrical/Computer Engineering or Computer Science
Master's Degree preferred but not required

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