CPU Physical Implementation Lead

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Job description

Job Title: CPU Physical Implementation Lead
Location: Austin, TX
Duration: Direct Hire

Summary:

Our client is the 4th largest fabless semiconductor company leading the market in chipset sales for Smartphone, Smart TVs, Voice Assistant Devices (VAD), Android tablets, feature phones, and optical disc products.

Responsibilities:

In this highly visible role, you will be responsible for hands-on high performance CPU implementation (RTL to GDSII) in advanced nodes. Develop CPU implementation recipes via design of experiments (DOE) to achieve the highest power efficiency in the industry. Drive micro-architecture changes, custom library development, metal-stack definition to help achieve best in class implementation. Perform trials to optimize floorplan, tune optimization recipe to meet power/performance/area goals and sign-off requirements. Perform block level floorplanning, pin placement and power grid implementation. Execute RTL2GDSII implementation flow. Run physical verification flows (DRC/LVS/EM/IR), implement fixes to meet the requirements. Implement ECO's to address functional bugs, timing and physical verification violations. Responsible for generation and maintenance of block level STA constraints. Responsible for physical deliverables (lef/def/gdsii) and support successful integration of blocks into SOC.

Qualifications:
5+ years of hands on experience in physical design of high performance CPU design with frequencies > 2 Ghz.
Experienced in hierarchical design, budgeting, multiple voltage domains and multiple clock domains.
Hands-on experience with different clocking techniques including CTS, multi-source CTS, concurrent clock and datapath optimization.
Experienced in working on advanced finfet process nodes (16nm) and developing implementation flows tuned to meet sign-off requirements.
Sign-off experience meeting signal integrity, power integrity, and DFM requirements.
Strong skills with Cadence or Synopsys Implementation tools.
Solid understanding of STA and timing constraints.
Strong scripting skills in tcl, perl, or python.

Plus:

ARM CPU implementation experience
Experience with structured datapath implementation.
STA & timing closure
IR Drop analysis (Static & Dynamic)

IND123