Senior FPGA / ASIC Design Verification Engineer (Lead)

---

Job description

Company:

cPacket Networks is a leading provider of next-generation network performance monitoring and packet broker solutions that are the leading edge foundation for a secure and reliable autonomous network. cPacket provides unprecedented network visibility reducing security risk and simplifying security architecture for Fortune 1000 companies - the network visibility you can trust.

Our story:

At cPacket, we work hard and play hard. We handle complex challenges like pros, we're not afraid to take risks, we learn fast, and we're experts in our field. Together, we're redefining the network performance industry. If you're curious, intelligent and passionate about making a meaningful impact, cPacket is the place for you. Our world-class engineering team includes software and hardware engineers, FPGA / ASIC design and verification engineers, and technologists with depth and expertise in the networking industry. If you like challenges, you'll love it at cPacket because we're solving tough problems every day. We're positioned to grow big and we are always pressing forward. We are committed to growth - both professionally and personally.

Responsibilities and Duties:

As a key member of our FPGA / ASIC team, you will verify the design and implementation of the industry's leading network monitoring devices.

• Lead the FPGA / ASIC design verification function for cPacket, including establishing long term strategy and vision, and more immediate implementation plans.
• Responsible for hands-on verification of FPGA / ASIC designs using state of the art verification methodologies such as UVM.
• Develop and integrate current and future designs into UVM environments.
• Document, and execute test plans on various platforms for designs under test.
• Integrate verification into continuous integration flow and into CI tools like TeamCity.

Qualifications and Skills:

• Bachelor's degree in EE/CS/CE or equivalent, with 10+ years of relevant experience.
• UVM and SystemVerilog expertise.
• Strong debugging, troubleshooting and analytical skills.
• Strong communication skills and collaborative attitude.
• Self-starter, and motivated to champion continuous improvement and positive team culture.
• Python experience is desirable.
• Networking and packet processing experience is a plus.